You'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure.

- 5+ years in physical synthesis or logic design implementation - Expert-level use of Fusion Compiler - Strong SDC constraint authoring and management skills - Experience with physical-aware synthesis flows and P&R hand-off - Working knowledge of STA (PrimeTime) - Proficiency in Tcl; Python scripting a strong plus - At least one tape-out on 7nm or below